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[AK4345]
AK4345
100dB 96kHz 24-Bit Stereo 3.3V DAC with DIT
GENERAL DESCRIPTION The AK4345 is a 24bit low voltage and low power stereo DAC with an integrated Digital Audio Interface Transmitter. The AK4345 uses an Advanced Multi-Bit architecture, which achieves 100dB dynamic range at 3.3V operation. The AK4345 integrates both switched-capacitor and continuous time filters, enabling performance for systems that have excessive clock jitter. The output voltage level can be set as high as 1Vrms. The AK4345 is offered in a space saving 16pin TSSOP package. FEATURES Sampling Rate: 8kHz 96kHz 24-Bit 8 times FIR Digital Filter SCF with high tolerance to clock jitter Single-ended output buffer Digital de-emphasis for 32kHz, 44.1kHz, 48kHz sampling I/F Format: 24-Bit MSB justified, 16/24-Bit LSB justified, I2S Compatible Master Clock: 512/768/1024/1536fs for Half Speed (8kHz 24kHz) 256/384/512/768fs for Normal Speed (8kHz 48kHz) 128/192/256/384fs for Double Speed (48kHz 96kHz) P Interface: 4-wire/3-wire DIT Bypass mode CMOS Input Level THD+N: -90dB DR, S/N: 100dB DAC output voltage level: 1Vrms (@VDD=3.3V) DIT - AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible - 1-channel Transmission output - 42-bit Channel Status Buffer Power Supply: 2.7 to 3.6V Ta = -20 85C 16pin TSSOP
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[AK4345]
MCLK CSN CCLK CDTI CDTO
P Interface De-emphasis Control DIT 8X Interpolator 8X Interpolator Modulator Modulator
VDD
Clock Divider
VSS VCOM
TX
SDTI1
LRCK BICK
Audio Data Interface
SCF LPF SCF LPF
LOUT
ROUT
TEST
PDN
Figure 1. AK4345 Block Diagram (Mode= "0")
MCLK CSN CCLK CDTI
P Interface De-emphasis Control DIT 8X Interpolator 8X Interpolator Modulator Modulator
VDD
Clock Divider
VSS VCOM
TX
SDTI2 SDTI1 LRCK BICK
Audio Data Interface
SCF LPF SCF LPF
LOUT
ROUT
TEST
PDN
Figure 2. AK4345 Block Diagram (Mode= "1")
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[AK4345]
Ordering Guide
AK4345ET AKD4345 -20 +85C 16pin TSSOP (0.65mm pitch) Evaluation Board for AK4345
Pin Layout
MCLK BICK SDTI1 LRCK PDN CSN CCLK CDTI 1 2 3 4 5 6 7 8 16 15 14 TX CDTO/ SDTI2 VDD VSS VCOM LOUT ROUT TEST1
AK4345 Top View
13 12 11 10 9
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[AK4345]
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name MCLK BICK SDTI1 LRCK PDN CSN CCLK CDTI TEST1 ROUT LOUT VCOM VSS VDD CDTO SDTI2 TX I/O I I I I I I I I I O O O O I O Function Master Clock Input Pin Audio Serial Data Clock Pin Audio Serial Data Input Pin1 Input Channel Clock Pin Full Power Down Mode Pin "L" : Power down, "H" : Power up Chip Select Pin Control Data Clock Pin Control Data Input Pin TEST Pin This pin must be OPEN. Rch Analog Output Pin, The output is "Hi-Z" when PDN pin = "L". Lch Analog Output Pin, The output is "Hi-Z" when PDN pin = "L". Common Voltage Output Pin, 0.5 x VDD Normally connected to VSS with a 4.7F (min. 1F, max. 10F) electrolytic Capacitor. The output is "L" when PDN pin = "L". Ground Pin Power Supply Pin, 2.7 3.6V Control Data Output Pin, The output is "Hi-Z" when PDN pin = "L". Audio Serial Data Input Pin2 Transmit Channel Output Pin, The output is "L" when PDN pin = "L".
Note: All digital input pins should not be left floating.
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[AK4345]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1) Parameter Power Supply Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Temperature (Powered applied) Storage Temperature Symbol VDD IIN VIND Ta Tstg min -0.3 -0.3 -20 -65 max 4.6 10 VDD+0.3 85 150 Units V mA V C C
(Note 2)
Note 1. All voltages with respect to ground. Note 2. MCLK, BICK, SDTI1, LRCK, PDN, CSN, CCLK, CDTI, SDTI2 WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1) Parameter Power Supply Note 1. All voltages with respect to ground. WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. Symbol VDD min 2.7 typ 3.3 max 3.6 Units V
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[AK4345]
ANALOG CHARACTERISTICS (Ta=25C; VDD=3.3V; VSS=0V; fs=44.1kHz, 96kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz 20kHz at fs=44.1kHz, 20Hz 40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max Units Dynamic Characteristics (GAIN bit= "1") : Resolution 24 Bits 0dBFS -90 -80 dB THD+N fs=44.1kHz -60dBFS -37 dB BW=20kHz 0dBFS -88 dB fs=96kHz -60dBFS -34 dB BW=40kHz DR (-60dBFS with A-weighted) 92 100 dB S/N (A-weighted) 92 100 dB Interchannel Isolation 80 100 dB DC Accuracy: Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 100 ppm/C Output Voltage: GAIN bit= "1" (Note 3) 2.60 2.8 3.0 Vpp Output Voltage: GAIN bit="0" (Note 4) 2.05 2.2 2.35 Vpp Load Resistance (Note 5) 10 k Load Capacitance 25 pF Power Supplies Power Supply Current Normal Operation (PDN pin = "H", fs=44.1kHz) (Note 6) 7.0 mA Normal Operation (PDN pin = "H", fs=96kHz) (Note 6) 8.5 12.8 mA Full Power-down mode (PDN pin = "L") (Note 7) 10 50 A
Note 3. Full-scale voltage (0dB). Output voltage scales with the voltage of VDD, Vout = 0.85 x VDD (typ). Note 4. Full-scale voltage (0dB). Output voltage scales with the voltage of VDD, Vout = 0.67 x VDD (typ). Note 5. For AC-load. Note 6. RSTN bit= "1", PW bit= "1", TX pin: open. When TX pin = 20pF, power supply current (IDD@3.3V) is 9.0mA(typ)@fs= 96kHz. Note 7. All digital input pins are fixed to VDD or VSS.
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FILTER CHARACTERISTICS (Ta=25C; VDD=2.7 3.6V; fs=44.1kHz; DEM1 bit= "0", DEM0 bit= "1") Parameter Symbol min DAC Digital Filter: Passband (Note 8) 0.05dB PB 0 -6.0dB Stopband (Note 8) SB 24.1 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 9) GD Digital Filter + SCF + CTF: Frequency Response 0 20kHz FR 40kHz (Note 10) -
typ
max 20.0 0.01
Units kHz kHz kHz dB dB 1/fs dB dB
22.05
24.0 0.1 0.2
-
Note 8. The passband and stopband frequencies scale with fs (system sampling rate). Note 9. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both channels to input register to the output of analog signal. Note 10. At fs=96kHz.
DC CHARACTERISTICS
(Ta=25C; VDD=2.7 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout=-80A) Low-Level Output Voltage (Iout=80A) Input Leakage Current Symbol VIH VIL VOH1 VOL1 Iin min 70%VDD VDD-0.4 typ max 30%VDD 0.4 10 Units V V V V A
TX CHARACTERISTICS
(Ta=25C; VDD=2.7 3.6V) Parameter High-Level Output Voltage ( Iout=-400A) Low-Level Output Voltage ( Iout=400A) Load Capacitance Symbol VOH2 VOL2 CL min VDD-0.4 typ max 0.4 50 Units V V pF
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[AK4345]
SWITCHING CHARACTERISTICS (Ta=25C; VDD=2.7 3.6V; CL = 20pF) Parameter Symbol min Master Clock Frequency Half Speed Mode (512/768/1024/1536fs) fCLK 4.096 Normal Speed Mode (256/384/512/768fs) fCLK 2.048 Double Speed Mode (128/192/256/384fs) fCLK 6.144 Duty Cycle dCLK 40 LRCK Frequency Half Speed Mode (DFS1-0 = "10") fsh 8 Normal Speed Mode (DFS1-0 = "00") fsn 8 Double Speed Mode (DFS1-0 = "01") fsd 48 Duty Cycle dCLK 45 Audio Interface Timing BICK Period 1/128fs tBCK Half Speed Mode 1/128fs tBCK Normal Speed Mode 1/64fs tBCK Double Speed Mode 70 tBCKL BICK Pulse Width Low 70 tBCKH Pulse Width High 40 tBLR BICK "" to LRCK Edge (Note 11) 40 tLRB LRCK Edge to BICK "" (Note 11) 40 tSDH SDTI Hold Time 40 tSDS SDTI Setup Time Control Interface Timing 200 CCLK Period tCCK 80 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 40 CDTI Setup Time tCDS 40 CDTI Hold Time tCDH 150 CSN "H" Time tCSW 150 CSN "" to CCLK "" tCSS 50 tCSH CCLK "" to CSN "" tDCD CDTO Delay tCCZ CSN "" to CDTO Hi-Z
Power-Down & Reset Timing PDN Pulse Width (Note 12) tPD 4
typ
max 36.864 36.864 36.864 60 24 48 96 55
Units MHz MHz MHz % kHz kHz kHz %
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms/F
45 70
Note 11. BICK rising edge must not occur at the same time as LRCK edge. Note 12. The AK4345 can be reset by bringing PDN pin = "L". The PDN pulse width is proportional to the value of the capacitor (C) connected to VCOM pin. tPD = 4000x C. When C = 4.7F, tPD is 19ms(min). The value of the capacitor (C) connected with VCOM pin should be 1F C 10F.
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[AK4345]
Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
MCLK
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Figure 3. Clock Timing
LRCK tBLR tLRB
VIH VIL
BICK tSDS tSDH
VIH VIL
SDTI
VIH VIL
Figure 4. Serial Interface Timing
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[AK4345]
VIH CSN tCSS tCCK tCCKL tCCKH CCLK tCDH VIH VIL tCDS VIL
CDTI
C1
C0
R/W
A4
VIH VIL
CDTO
Hi-Z
Figure 5. WRITE/READ Command Input Timing in 3-wire/4-wire serial mode
tCSW VIH CSN tCSH VIH VIL VIL
CCLK
CDTI
D3
D2
D1
D0
VIH VIL
CDTO
Hi-Z
Figure 6. WRITE Data Input Timing in 3-wire/4-wire serial mode
VIH CSN VIL
CCLK
VIH VIL
CDTI
A1
A0
VIH VIL tDCD
CDTO
Hi-Z
D7
D6
D5
50%VDD
Figure 7. READ Data Output Timing 1 in 4-wire serial mode
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[AK4345]
tCSW CSN VIH VIL tCSH CCLK VIH VIL
CDTI
VIH VIL tCCZ
CDTO
D3
D2
D1
D0
Hi-Z
50%VDD
Figure 8. READ Data Output Timing 2 in 4-wire serial mode
tPD
PDN
VIL
Figure 9. Power-Down & Reset Timing
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[AK4345]
OPERATION OVERVIEW
System Clock
The external clocks, which are required to operate the AK4345, are MCLK, BICK and LRCK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. The MCLK frequency is detected from the relation between MCLK and LRCK automatically. The Half speed, the Normal speed and the Double speed mode are selected with the DFS1-0 bits (Table 1). The sampling speed mode is set depending on the MCLK frequency automatically for Auto mode (DFS1 bit = DFS0 bit = "1") (Table 2). The AK4345 is automatically placed in the reset mode when MCLK stops in the normal operation mode (PDN pin = "H"), and the analog output becomes the VCOM voltage. After MCLK is input again, the AK4345 is powered up. After exiting reset by PDN pin at power-up etc., the AK4345 is in the reset mode until MCLK and LRCK are input.
Mode Normal Speed Double Speed Half Speed Auto
DFS1 0 0 1 1
DFS0 fs 0 8 48kHz 1 48 96kHz 0 8 24kHz 1 8 96kHz Table 1. System Clock Example Sampling Speed Mode Normal Speed Double Speed Half Speed Table 2. Auto Mode
MCLK Frequency 256/384/512/768fs 128/192/256/384fs 512/768/1024/1536fs Table 2
MCLK Frequency 512/768fs 128/192/256/384fs 1024/1536fs
Fs 8 48kHz 48 96kHz 8 24kHz
Audio Interface Format
The Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF1-0 bits as shown in Table 3 can select four serial data modes. In all modes the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 3 can be used for 16bit I2S Compatible format by zeroing the unused LSBs at BICK 48fs or BICK = 32fs. Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 SDTI Format 0 16bit, LSB justified 1 24bit, LSB justified 0 24bit, MSB justified 1 16/24bit, I2S Compatible Table 3. Audio Interface Format BICK 32fs 48fs 48fs 48fs or 32fs Figure Figure 10 Figure 11 Figure 12 Figure 13
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[AK4345]
LRCK
0123 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1
BICK(32fs) SDTI(i) BICK(64fs) SDTI(i)
Don't Care 15 14 13 12 10 Don't Care 15 14 13 12 210 15 14 13 0123 7 6 5 4 3 2 1 0 15 14 13 17 18 19 20 31 0 1 2 3 7 6 5 4 3 2 1 0 15 17 18 19 20 31 0 1
SDTI-15:MSB, 0:LSB Lch Data Rch Data
Figure 10. Mode 0 Timing
LRCK
012 89 24 31 0 1 2 89 24 31 0 1
BICK(64fs) SDTI(i)
Don't Care 23:MSB, 0:LSB Lch Data Rch Data 23 8 10 Don't Care 23 8 10
Figure 11. Mode 1 Timing
LRCK
012 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1
BICK(64fs) SDTI(i)
23 22 4 3 2 1 0 Don't Care 23 22 43210 Don't Care 23
23:MSB, 0:LSB Lch Data Rch Data
Figure 12. Mode 2 Timing
LRCK
0123 21 22 23 24 25 012 21 22 23 24 25 01
BICK(64fs) SDTI(i)
23 22 4 3 2 1 0 Don't Care 23 22 43210 Don't Care
23:MSB, 0:LSB Lch Data Rch Data
Figure 13. Mode 3 Timing
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[AK4345]
Data Transmission Format
Data transmitted on the TX outputs is formatted in blocks as shown in Figure 14. Each block consists of 192 frames. A frame of data contains two sub-frames. A sub-frame consists of 32 bits of information. Each received data bit is coded using a bi-phase mark encoding as a two binary state symbol. The preambles violate bi-phase encoding so they may be differentiated from data. In bi-phase encoding, the first state of an input symbol is always the inverse of the last state of the previous data symbol. For a logic 0, the second state of the symbol is the same as the first state. For a logic 1, the second state is the opposite of the first. Figure 15 illustrates a sample stream of 8 data bits encoded in 16 symbol states.
M Channel 1 W Channel 2 B Channel 1 W Channel 2 M Channel 1 W Channel 2 Sub-frame Frame 191 Sub-frame Frame 1
Frame 0
Figure 14. Block format
0 1 1 0 0 0 1 0
Figure 15. A biphase-encoded bit stream The sub-frame is defined in Figure 16 below. Bits 0-3 of the sub-frame represent a preamble for synchronization. There are three preambles. The block preamble, B, is contained in the first sub-frame of Frame 0. The channel 1 preamble, M, is contained in the first sub-frame of all other frames. The channel 2 preamble, W, is contained in all of the second sub-frames. Table 4 below defines the symbol encoding for each of the preambles. Bits 4-27 of the sub-frame contain the 24 bit audio sample in 2's complement format with bit 27 as the most significant bit. For 16 bit mode, Bits 4-11 are all 0. Bit 28 is the validity flag. This is "H" if the audio sample is unreliable. Bit 29 is a user data bit. Frame 0 contains the first bit of a 192 bit user data word. Frame 191 contains the last bit of the user data word. Bit 30 is a channel status bit. Again frame 0 contains the first bit of the 192 bit word with the last bit in frame 191. Bit 31 is an even parity bit for bits 4-31 of the sub-frame.
0
34 L Sync S B
Audio sam ple
Figure 16. Sub-frame format
27 28 29 30 31 M SVUCP B
The block of data contains consecutive frames transmitted at a state-bit rate of 64 times the sample frequency, fs. For stereophonic audio, the left or A channel data is in channel 1 while the right or B data is in channel 2. For monophonic audio, channel 1 contains the audio data. Preamble B M W Preceding state = 0 11101000 11100010 11100100 Preceding state = 1 00010111 00011101 00011011
Table 4. Sub-frame preamble encoding
Channel Status bit
In the consumer mode (bit0 = "0"), bits20-23(audio channel) must be controlled by the CS20 bit. When the CS20 bit is "1", the AK4345 corresponds to "stereo mode", bits20-23 are set to "1000"(left channel) in sub-frame 1, and is set to "0100"(right channel) in sub-frame 2. When the CS20 bit is "0", bits20-23 is set to "0000" in both sub-frame 1 and sub-frame 2. MS0635-E-00 - 14 2007/06
[AK4345]
De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15s) and is controlled by DEM0 and DEM1. In double speed and quad speed mode, the digital de-emphasis filter is always off. DEM1 0 0 1 1 DEM0 0 1 0 1 Mode 44.1kHz OFF 48kHz 32kHz (default)
Table 5. De-emphasis Filter Control (Normal Speed Mode)
Power-down
The AK4345 is placed in the power-down mode by bringing PDN pin = "L". and the digital filter is reset at the same time. This reset should always be done after power up.
PDN
Internal State D/A In (Digital)
GD
(1)
Normal Operation
Power-down
Normal Operation
"0" data
(2) (4) (3) (4)
GD
(2)
D/A Out (Analog)
Clock In
MCLK, BICK, LRCK
(5) Don't care (6)
External MUTE
Mute ON
Notes: (1) PDN pin should be "L" for 19ms or more when an electrolytic capacitor 4.7F is attached between VCOM pin and VSS. (2) The analog output corresponding to digital input has the group delay (GD). (3) When PDN pin = "L", the analog output is Hi-Z. (4) Click noise occurs in 3 4LRCK at both edges ( ) of PDN signal. This noise is output even if "0" data is input. (5) The external clocks (MCLK, BICK and LRCK) can be stopped in the power down mode (PDN pin = "L"). (6) Please mute the analog output externally if the click noise (4) influences system application. The timing example is shown in this figure. Figure 17. Power-down/up sequence example
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[AK4345]
Reset Function
(1) Reset by RSTN bit When RSTN bit =0, DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage Figure 18 shows the example of reset by RSTN bit.
RSTN bit
3~4/fs (6) 2~3/fs (6)
Internal RSTN bit Internal State D/A In (Digital) (1) D/A Out (Analog)
Clock In
MCLK,LRCK,BICK
Normal Operation
Digital Block P d
Normal Operation
"0" data GD GD
(3)
(2) (4)
Don't care
(3)
(1)
Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs go to VCOM voltage (VDD/2). (3) Click noise occurs at the edges(" ") of the internal timing of RSTN bit. This noise is output even if "0" data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN bit = "0"). (5) There is a delay, 3~4/fs from RSTN bit "0" to the internal RSTN bit "0", and 2~3/fs from RSTN bit "1" to the internal RSTN bit "1". Figure 18. Reset Sequence Example1
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[AK4345]
(2) RESET by MCLK stop (PDN pin = "H") When MCLK stops, DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage.
PDN pin
Internal State D/A In (Digital) D/A Out (Analog)
Clock In
MCLK, BICK, LRCK
(1)
Power-down
Normal Operation
Reset
Normal Operation
Power-down GD Hi-Z
(3) (2) (4) (4) (5) MCLK Stop
VCOM GD
(2)
(4)
External MUTE
(6)
(6)
(6)
Notes: (1) PDN pin should be "L" for 19ms or more when an electrolytic capacitor 4.7F is attached between VCOM pin and VSS. (2) The analog output corresponding to digital input has the group delay (GD). (3) The digital data can be stopped. The click noise after MCLK is input again by inputting the "0" data to this section can be reduced. (4) Click noise occurs in 3 4LRCK at both edges ( ) of PDN signal, MCLK inputs and MCLK stops. This noise is output even if "0" data is input. (5) The external clocks (BICK and LRCK) can be stopped in the power down mode (MCLK stop). (6) Please mute the analog output externally if the click noise (4) influences system application. The timing example is shown in this figure. Figure 19. Reset Sequence Example 2
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[AK4345]
P Control Interface
The AK4345 can select 4-wire P I/F mode (MODE bit = "0") or 3-wire P I/F mode (MODE bit = "1").
1.4-wire P I/F mode (MODE bit = "0", default) The internal registers may be either written or read by the 4-wire P interface pins: CSN, CCLK, CDTI and CDTO. The data on this interface consists of Chip address (2bits, C1/0; fixed to "01"), Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low transition of CSN. CSN should be set to "H" once after 16 CCLKs. For read operations, the CDTO output goes high impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN pin = "L" resets the registers to their default values.
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK
CDTI WRITE CDTO CDTI READ CDTO
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
C1-C0: R/W: A4-A0: D7-D0:
Chip Address: (Fixed to "01") READ/WRITE (0:READ, 1:WRITE) Register Address Control Data Figure 20. 4-wire Serial Control I/F Timing
*When the AK4345 is in the power down mode (PDN pin = "L") or the MCLK is not provided, writing into the control register is inhibited.
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[AK4345]
2.3-wire P I/F mode (MODE bit = "1") Internal registers may be written by 3-wire P interface pins, CSN, CCLK and CDTI. The data on this interface consists of Chip Address (2bits, C1/0; fixed to "01"), Read/Write (1bit; fixed to "1", Write only), Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). AK4345 latches the data on the rising edge of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by 16th CCLK after a high to low transition of CSN. CSN should be set to "H" once after 16 CCLKs for each address. The clock speed of CCLK is 5MHz (max).
PDN pin = "L" resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers are not initialized.
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: R/W: A4-A0: D7-D0:
Chip Address (Fixed to "01") READ/WRITE (Fixed to "1", Write only) Register Address Control Data
Figure 21. Control I/F Timing *The AK4345 does not support the read command and chip address. C1/0 and R/W are fixed to "011" *When the AK4345 is in the power down mode (PDN pin = "L") or the MCLK is not provided, writing into the control register is inhibited.
DAC and DIT input select
The AK4345 can select 4-wire P I/F mode (MODE bit = "0") or 3-wire P I/F mode (MODE bit = "1"). In 3-wire P I/F mode, the AK4345 can select the input data of DAC and DIT from SDTI1 or SDTI2 data. MODE 0 1 1 1 1 SEL1 x 0 0 1 1 SEL0 x 0 1 0 1 P I/F 4-wire 3-wire 3-wire 3-wire Reserved DAC input SDTI1 SDTI1 SDTI2 SDTI2 DIT input SDTI1 SDTI1 SDTI2 Bypass (x: Don't care) Table 6. DAC and DIT Input
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[AK4345]
Register Map
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H Notes: For addresses from 0AH to 1FH, data must not be written. When PDN pin goes "L", the registers are initialized to their default values. When RSTN bit goes "0", the only internal timing is reset and the registers are not initialized to their default values. All data can be written to the register even if PW or RSTN bit is "0". The bits shown as "0" should be written "0" and the bits shown as "1" should be written "1". Register Name Control 1 Control 2 Control 3 TX Channel Status Byte0 Channel Status Byte1 Channel Status Byte2 Channel Status Byte3 Channel Status Byte4 Channel Status Byte5 D7 1 0 0 0 CS7 CS15 CS23 CS39 CS39 0 D6 0 1 0 0 CS6 CS14 CS22 CS38 CS38 0 D5 0 0 0 0 CS5 CS13 CS21 CS37 CS37 0 D4 0 DFS1 INVL 0 CS4 CS12 CS20 CS36 CS36 0 D3 DIF1 DFS0 INVR 0 CS3 CS11 CS19 CS35 CS35 0 D2 DIF0 DEM1 MODE 0 CS2 CS10 CS18 CS34 CS34 0 D1 PW DEM0 SEL1 V CS1 CS9 CS17 CS33 CS33 CS41 D0 RSTN GAIN SEL0 TXE CS0 CS8 CS16 CS32 CS32 CS40
Register Definitions
Addr 00H Register Name Control 1 R/W Default 1 0 0 0 D7 1 D6 0 D5 0 D4 0 R/W 1 1 1 1 D3 DIF1 D2 DIF0 D1 PW D0 RSTN
RSTN: Internal timing reset control 0: Reset. All registers are not initialized. 1: Normal Operation When MCLK frequency or DFS changes the click noise occurs. It can be reduced by RSTN bit. PW: Power down control 0: Power down. All registers are not initialized. 1: Normal Operation DIF1-0: Audio data interface formats (Table 3) Initial: "11", Mode 3
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[AK4345]
Addr 01H
Register Name Control 2 R/W Default
D7 0 0
D6 1 1
D5 0 0
D4 DFS1 R/W 1
D3 DFS0 1
D2 DEM1 0
D1 DEM0 1
D0 GAIN 1
DEM1-0: De-emphasis Response (Table 5) Initial: "01", OFF DFS1-0: Sampling speed control 00: Normal speed 01: Double speed 10: Half speed 11: Auto (default) When changing between Normal/Double Speed Mode and Half Speed Mode, some click noise occurs. GAIN: Output Voltage scale 0: Vout = 0.67 x VDD (typ) at Full-scale voltage (0dB) . 1: Vout = 0.85 x VDD (typ) at Full-scale voltage (0dB) .
Register Name 02H Control 3 R/W Default
D7 0 0
D6 0 0
D5 0 0
D4 INVL R/W 0
D3 INVR 0
D2 MODE 0
D1 SEL1 0
D0 SEL0 0
INVR: Inverting Lch Output Polarity 0: Normal Output 1: Inverted Output INVL: Inverting Rch Output Polarity 0: Normal Output 1: Inverted Output MODE: Mode Control 0: 4 wire mode 1: 3 wire mode SEL1-0: DAC and DIT input 00: SDTI1 input 01: SDTI2 input 10: SDTI2 input (DIT Bypass) 11: Reserved SEL1-0 bits are disabled in 4-wire P I/F mode (MODE bit = "0"). SDTI1 data is input to both DAC and DIT.
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[AK4345]
Register Name 03H TX R/W Default V: Validity Flag 0: Valid 1: Invalid
D7 1 1
D6 0 0
D5 0 0
D4 0 R/W 0
D3 0 0
D2 0 0
D1 V 0
D0 TXE 1
TXE: TX output 0: "L" 1: Normal Operation Register Name 04H 05H 06H 07H 08H 09H Channel Status Byte0 Default Channel Status Byte1 Default Channel Status Byte2 Default Channel Status Byte3 Default Channel Status Byte4 Default Channel Status Byte5 Default D7 CS7 0 CS15 0 CS23 0 CS31 0 CS39 0 0 0 D6 CS6 0 CS14 0 CS22 0 CS30 0 CS38 0 0 0 D5 CS5 0 CS13 0 CS21 0 CS29 0 CS37 0 0 0 D4 CS4 0 CS12 0 CS20 0 CS28 0 CS36 0 0 0 D3 CS3 0 CS11 0 CS19 0 CS27 0 CS35 0 0 0 D2 CS2 1 CS10 0 CS18 0 CS26 0 CS34 0 0 0 D1 CS1 0 CS9 0 CS17 0 CS25 0 CS33 0 CS41 0 D0 CS0 0 CS8 0 CS16 0 CS24 0 CS32 0 CS40 0
CS7-0: Transmitter Channel Status Byte 0 Default: "00000100" CS39-8: Transmitter Channel Status Byte 4-1 Default: "00000000" CS41-CS40: Transmitter Channel Status Byte 5 Default: "00000000", D7-D2 bits should be written "0".
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[AK4345]
SYSTEM DESIGN
Figure 22 and Figure 23 shows the system connection diagram. The evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.
Master Clock 64fs 24bit Audio Data fs Reset & Power down Micro Controller
300 1 2 3 4 5 6 7 8 MCLK BICK SDTI LRCK PDN CSN CCLK CDTI TX CDTO VDD 16 15 14 0.1u 13 4.7u VCOM LOUT ROUT TEST1 12 11 10 9 +
Optic transmitting module
+
10u
Analog Supply 2.7 to 3.6V
AK4345
VSS
Lch Out Rch Out
Digital Ground
Analog Ground
Figure 22. Typical Connection Diagram (Mode bit = "0", 4 wire mode )
24bit Audio Data2 Master Clock 64fs 24bit Audio Data1 fs Reset & Power down Micro Controller
300 1 2 3 4 5 6 7 8 MCLK BICK SDTI LRCK PDN CSN CCLK CDTI TX SDTI2 VDD 16 15 14 0.1u 13 4.7u VCOM LOUT ROUT TEST1 12 11 10 9 + + 10u
Optic transmitting module
Analog Supply 2.7 to 3.6V
AK4345
VSS
Lch Out Rch Out
Digital Ground
Analog Ground
Figure 23. Typical Connection Diagram (Mode bit = "1", 3 wire mode )
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[AK4345]
1. Grounding and Power Supply Decoupling The AK4345 requires careful attention for power supply and grounding arrangements. VDD is usually supplied from the analog supply in the system. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4345 as possible, with the small value ceramic capacitor being the closest. 2. Voltage Reference The differential Voltage between VDD and VSS sets the analog output range. VCOM is used as a common voltage of the analog signal. VCOM pin is a signal ground of this chip. An electrolytic capacitor about 4.7F should be attached between VCOM pin and VSS. No load current may be drawn from VCOM pin. Especially, the ceramic capacitor should be connected to this pin as near as possible. 3. Analog Outputs The analog outputs are single-ended and centered around the VCOM voltage (0.5 x VDD). The output signal range is typically 2.8Vpp (typ@VDD=3.3V). The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage (0.5 x VDD) for 000000H (@24bit). DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few mV. Figure 24 shows an example of the external LPF with 2.8Vpp (1Vrms) output.
AK4345 10u
LOUT / ROUT
220
Analog Out 2.8Vpp (1Vrms)
1nF
22k
fc=723.4kHz, g=-0.013dB at 40kHz
Figure 24. External 1st order LPF Circuit Example
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[AK4345]
PACKAGE
16pin TSSOP (Unit: mm)
*5.00.08 1.07 +0.03 -0.07
16
9 *4.40.1 A 6.40.2 0.170.05 Detail A 0.07+0.03 -0.04 0-10 0.50.2 0.10
Epoxy Cu Solder (Pb free) plate
1 0.220.08
8 0.65
0.13 M
Seating Plane
NOTE: Dimension "*" does not include mold flash.
Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment:
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[AK4345]
MARKING
AKM 4345ET XXYYY
1) 2)
3) 4)
Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4345ET Asahi Kasei Logo
REVISION HISTORY
Date (YY/MM/DD) 07/06/20 Revision 00 Reason First Edition Page Contents
IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.
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